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https://github.com/Pecusx/libretro-atari800.git
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R-type
319 lines
10 KiB
ArmAsm
319 lines
10 KiB
ArmAsm
| videl.asm - Atari Falcon specific port code
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| Copyright (c) 1997-1998 Petr Stehlik and Karel Rous
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| Copyright (c) 1998-2003 Atari800 development team (see DOC/CREDITS)
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| This file is part of the Atari800 emulator project which emulates
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| the Atari 400, 800, 800XL, 130XE, and 5200 8-bit computers.
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| Atari800 is free software; you can redistribute it and/or modify
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| it under the terms of the GNU General Public License as published by
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| the Free Software Foundation; either version 2 of the License, or
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| (at your option) any later version.
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| Atari800 is distributed in the hope that it will be useful,
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| but WITHOUT ANY WARRANTY; without even the implied warranty of
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| MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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| GNU General Public License for more details.
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| You should have received a copy of the GNU General Public License
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| along with Atari800; if not, write to the Free Software
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| Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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.globl _load_r,_save_r,_p_str_p
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*-------------------------------------------------------*
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.text
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*-------------------------------------------------------*
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.set none,-1
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*-------------------------------------------------------*
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*-------------------------------------------------------*
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.set plane_bits,0+0 | 0
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.set true_bit,0+2 | 2
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.set hires_bit,0+3 | 3
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.set vga_bit,0+4 | 4
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.set pal_bit,0+5 | 5
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.set os_bit,0+6 | 6
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.set compat_bit,0+7 | 7
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.set lace_bit,0+8 | 8
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*-------------------------------------------------------*
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*-------------------------------------------------------*
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.set bpl1,0+0
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.set bpl2,0+1
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.set bpl4,0+2
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.set bpl8,0+3
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*-------------------------------------------------------*
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.set true,1<<true_bit
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.set hires,1<<hires_bit
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.set vga,1<<vga_bit
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.set pal,1<<pal_bit
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.set os,1<<os_bit
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.set compat,1<<compat_bit
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.set lace,1<<lace_bit
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*-------------------------------------------------------*
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* Videl registers *
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*-------------------------------------------------------*
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.set RShift,0xFFFF8260
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.set RSpShift,0xFFFF8266
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.set RWrap,0xFFFF8210
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.set RSync,0xFFFF820A
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.set RCO,0xFFFF82C0
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.set RMode,0xFFFF82C2
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.set RHHT,0xFFFF8282
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.set RHBB,0xFFFF8284
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.set RHBE,0xFFFF8286
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.set RHDB,0xFFFF8288
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.set RHDE,0xFFFF828A
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.set RHSS,0xFFFF828C
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.set RHFS,0xFFFF828E
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.set RHEE,0xFFFF8290
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.set RVFT,0xFFFF82A2
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.set RVBB,0xFFFF82A4
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.set RVBE,0xFFFF82A6
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.set RVDB,0xFFFF82A8
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.set RVDE,0xFFFF82AA
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.set RVSS,0xFFFF82AC
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*-------------------------------------------------------*
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* Videl register file *
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*-------------------------------------------------------*
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*-------------------------------------------------------*
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.set patch_code,0+0 | fake modecode (describes register file)
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*-------------------------------------------------------*
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.set patch_size,0+2 | total display memory
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.set patch_width,0+6 | horizontal res
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.set patch_height,0+8 | vertical res
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.set patch_depth,0+10 | colour depth (bits per pixel)
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*-------------------------------------------------------*
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.set patch_RShift,0+12 | register file
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.set patch_RSync,0+13
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.set patch_RSpShift,0+14
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.set patch_RWrap,0+16
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.set patch_RCO,0+18
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.set patch_RMode,0+20
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.set patch_RHHT,0+22
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.set patch_RHBB,0+24
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.set patch_RHBE,0+26
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.set patch_RHDB,0+28
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.set patch_RHDE,0+30
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.set patch_RHSS,0+32
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.set patch_RHFS,0+34
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.set patch_RHEE,0+36
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.set patch_RVFT,0+38
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.set patch_RVBB,0+40
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.set patch_RVBE,0+42
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.set patch_RVDB,0+44
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.set patch_RVDE,0+46
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.set patch_RVSS,0+48
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*-------------------------------------------------------*
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.set patch_slen,0+50
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*-------------------------------------------------------*
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.set hz200,0x4ba
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.set vbcount,0x462
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*-------------------------------------------------------*
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* Load Videl registers *
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*-------------------------------------------------------*
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_load_r:
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*-------------------------------------------------------*
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* Register file pointer *
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*-------------------------------------------------------*
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move.l _p_str_p,a0
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*-------------------------------------------------------*
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* Allow previous VBlank changes to settle *
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*-------------------------------------------------------*
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moveq #5,d0
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add.l hz200.w,d0
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load_r_wait: nop
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cmp.l hz200.w,d0
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bne.s load_r_wait
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*-------------------------------------------------------*
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* Reset Videl for new register file *
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*-------------------------------------------------------*
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clr.w RSpShift.w
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*-------------------------------------------------------*
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* Lock exceptions *
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*-------------------------------------------------------*
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move.w sr,-(sp)
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or.w #0x700,sr
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*-------------------------------------------------------*
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* Load shift mode *
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*-------------------------------------------------------*
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cmp.w #2,patch_depth(a0)
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bne.s load_r_n2p
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move.b patch_RShift(a0),RShift.w
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bra.s load_r_d2p
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load_r_n2p: move.w patch_RSpShift(a0),RSpShift.w
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*-------------------------------------------------------*
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* Load line wrap *
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*-------------------------------------------------------*
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load_r_d2p: move.w patch_RWrap(a0),RWrap.w
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*-------------------------------------------------------*
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* Load sync *
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*-------------------------------------------------------*
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move.b patch_RSync(a0),RSync.w
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*-------------------------------------------------------*
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* Load clock *
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*-------------------------------------------------------*
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move.w patch_RCO(a0),RCO.w
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*-------------------------------------------------------*
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* Load mode *
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*-------------------------------------------------------*
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move.w patch_RMode(a0),RMode.w
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*-------------------------------------------------------*
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* Horizontal register set *
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*-------------------------------------------------------*
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move.w patch_RHHT(a0),RHHT.w
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move.w patch_RHBB(a0),RHBB.w
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move.w patch_RHBE(a0),RHBE.w
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move.w patch_RHDB(a0),RHDB.w
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move.w patch_RHDE(a0),RHDE.w
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move.w patch_RHSS(a0),RHSS.w
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move.w patch_RHFS(a0),RHFS.w
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move.w patch_RHEE(a0),RHEE.w
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*-------------------------------------------------------*
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* Vertical register set *
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*-------------------------------------------------------*
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move.w patch_RVFT(a0),RVFT.w
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move.w patch_RVBB(a0),RVBB.w
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move.w patch_RVBE(a0),RVBE.w
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move.w patch_RVDB(a0),RVDB.w
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move.w patch_RVDE(a0),RVDE.w
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move.w patch_RVSS(a0),RVSS.w
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*-------------------------------------------------------*
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* Restore exceptions *
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*-------------------------------------------------------*
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move.w (sp)+,sr
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*-------------------------------------------------------*
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* Re-synchronize display for new settings *
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*-------------------------------------------------------*
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move.w patch_code(a0),d1
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bsr videl_re_sync
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*-------------------------------------------------------*
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rts
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*-------------------------------------------------------*
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* Save Videl registers *
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*-------------------------------------------------------*
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_save_r:
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*-------------------------------------------------------*
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* Get Modecode *
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*-------------------------------------------------------*
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move #-1,-(sp)
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move #87,-(sp)
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trap #14
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addq #4,sp
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*-------------------------------------------------------*
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* Register file pointer *
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*-------------------------------------------------------*
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move.l _p_str_p,a0
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*-------------------------------------------------------*
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* Save Modecode *
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*-------------------------------------------------------*
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move.w d0,patch_code(a0)
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and.w #0b0001111,d0
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move.w d0,patch_depth(a0)
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*-------------------------------------------------------*
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* Lock exceptions *
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*-------------------------------------------------------*
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move.w sr,-(sp)
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or.w #0x700,sr
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*-------------------------------------------------------*
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* Save shift mode *
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*-------------------------------------------------------*
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move.b RShift.w,patch_RShift(a0)
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move.w RSpShift.w,patch_RSpShift(a0)
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*-------------------------------------------------------*
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* Save line wrap *
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*-------------------------------------------------------*
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move.w RWrap.w,patch_RWrap(a0)
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*-------------------------------------------------------*
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* Save sync *
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*-------------------------------------------------------*
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move.b RSync.w,patch_RSync(a0)
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*-------------------------------------------------------*
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* Save clock *
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*-------------------------------------------------------*
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move.w RCO.w,patch_RCO(a0)
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*-------------------------------------------------------*
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* Save mode *
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*-------------------------------------------------------*
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move.w RMode.w,patch_RMode(a0)
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*-------------------------------------------------------*
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* Horizontal register set *
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*-------------------------------------------------------*
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move.w RHHT.w,patch_RHHT(a0)
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move.w RHBB.w,patch_RHBB(a0)
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move.w RHBE.w,patch_RHBE(a0)
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move.w RHDB.w,patch_RHDB(a0)
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move.w RHDE.w,patch_RHDE(a0)
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move.w RHSS.w,patch_RHSS(a0)
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move.w RHFS.w,patch_RHFS(a0)
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move.w RHEE.w,patch_RHEE(a0)
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*-------------------------------------------------------*
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* Vertical register set *
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*-------------------------------------------------------*
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move.w RVFT.w,patch_RVFT(a0)
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move.w RVBB.w,patch_RVBB(a0)
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move.w RVBE.w,patch_RVBE(a0)
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move.w RVDB.w,patch_RVDB(a0)
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move.w RVDE.w,patch_RVDE(a0)
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move.w RVSS.w,patch_RVSS(a0)
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*-------------------------------------------------------*
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* Restore exceptions *
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*-------------------------------------------------------*
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move.w (sp)+,sr
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rts
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*-------------------------------------------------------*
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videl_re_sync:
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*-------------------------------------------------------*
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* Decode new modecode *
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*-------------------------------------------------------*
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btst #compat_bit,d1
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bne.s idel_re_sync_nsync
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cmp.w #none,d1
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beq.s idel_re_sync_nsync
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and.w #0b111,d1
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cmp.w #bpl2,d1
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beq.s idel_re_sync_nsync
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*-------------------------------------------------------*
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* Reset Videl for re-sync *
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*-------------------------------------------------------*
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idel_re_sync_sync: move.w RSpShift.w,d1
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clr.w RSpShift.w
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*-------------------------------------------------------*
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* Wait for at least 1 VBlank period *
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*-------------------------------------------------------*
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moveq #2,d0
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add.l vbcount.w,d0
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moveq #9,d2
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add.l hz200.w,d2
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idel_re_sync_lp: nop
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cmp.l vbcount.w,d0
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beq.s idel_re_sync_stop
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cmp.l hz200.w,d2
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bne.s idel_re_sync_lp
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*-------------------------------------------------------*
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* Restore Videl mode *
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*-------------------------------------------------------*
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idel_re_sync_stop: move.w d1,RSpShift.w
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*-------------------------------------------------------*
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idel_re_sync_nsync: rts
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*-------------------------------------------------------*
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.bss
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*-------------------------------------------------------*
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_p_str_p: ds.l 1
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